Investigating Cache Parameters of x86 Family Processors
نویسندگان
چکیده
The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance engineering efforts. Unfortunately, the detailed parameters of the memory architecture are often not easily available, which makes it difficult to design experiments and evaluate results when the memory architecture is involved. To remedy this lack of information, we present experiments that investigate detailed parameters of the memory architecture, focusing on such information that is typically not available elsewhere.
منابع مشابه
Feedback-Directed Data Cache Optimizations for the x86
The vast majority of desktop microprocessors in use 1 today belong to a single architectural family, the x86. 2 The success of this architecture has led to a large 3 number of microarchitectures and a growing need to 4 evolve the ISA to meet the changing demands of 5 applications. Unfortunately, most compiled code 6 today targets the 486 or Pentium® , thereby missing 7 performance opportunities...
متن کاملImproving Memory Access Performance Using a Code Coalescing Unit
High clock frequencies combined with deep pipelining employed by many of the state-of-the-art processors have forced cache hit accesses to be multi-cycle operations. For many programs, untolerated load latencies account for a signiicant portion of total execution time. In this paper, we present a mechanism called the Code Coalescing Unit (CCU) that can identify and eliminate at run-time several...
متن کاملThe Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA
The potential performance of superscalar processors can be exploited only when processor is fed with sufficient instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs could not support instruction streaming beyond a basic block. In x86 processors, the split-line instruction problem worsens this ...
متن کاملDo Hardware Cache Flushing Operations Actually Meet Our Expectations?
We investigate how different categories of microarchitectural state on recent ARM and x86 processors can be used for covert timing channels and how effective architecture-provided mechanisms are in closing them. We find that in recent Intel processors there is no effective way for sanitising the state of the branch prediction unit and that, contrary to often held belief, flushing the translatio...
متن کاملEmpirical Study of Power Consumption of x86-64 Instruction Decoder
It has been a common myth that x86-64 processors suffer in terms of energy efficiency because of their complex instruction set. In this paper, we aim to investigate whether this myth holds true, and determine the power consumption of the instruction decoders of an x86-64 processor. To that end, we design a set of microbenchmarks that specifically trigger the instruction decoders by exceeding th...
متن کامل